Multithreading architecture

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Multithreaded architectures now appear across the entire range of computing devices, from the highest-performing general purpose devices to low-end embedded processors. Multithreading enables a processor core to more effectively utilize its computational resources, as a stall in one thread need not...

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Bibliographic Details
Main Author: Nemirovsky, Mario
Other Authors: Tullsen, Dean M.
Format: eBook
Language:English
Published: San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool, c2013.
Series:Synthesis digital library of engineering and computer science.
Synthesis lectures in computer architecture ; # 21.
Subjects:
Computer architecture.
Simultaneous multithreading processors.
multithreading
Online Access:Abstract with links to full text
Table of Contents:
  • Preface
  • 1. Introduction
  • 2. Multithreaded execution models
  • 2.1 Chip multiprocessors
  • 2.2 Conjoined core architectures
  • 2.3 Coarse-grain multithreading
  • 2.4 Fine-grain multithreading
  • 2.5 Simultaneous multithreading
  • 2.6 Hybrid models
  • 2.7 GPUs and warp scheduling
  • 2.8 Summary
  • 3. Coarse-grain multithreading
  • 3.1 Historical context
  • 3.2 A reference implementation of CGMT
  • 3.2.1 Changes to IF
  • 3.2.2 Changes to RD
  • 3.2.3 Changes to ALU
  • 3.2.4 Changes to MEM
  • 3.2.5 Changes to WB
  • 3.2.6 Swapping contexts
  • 3.2.7 Superscalar considerations
  • 3.3 Coarse-grain multithreading for modern architectures
  • 4. Fine-grain multithreading
  • 4.1 Historical context
  • 4.2 A reference implementation of FGMT
  • 4.2.1 Changes to IF
  • 4.2.2 Changes to RD
  • 4.2.3 Changes to ALU
  • 4.2.4 Changes to MEM
  • 4.2.5 Changes to WB
  • 4.2.6 Superscalar considerations
  • 4.3 Fine-grain multithreading for modern architectures
  • 5. Simultaneous multithreading
  • 5.1 Historical context
  • 5.2 A reference implementation of SMT
  • 5.2.1 Changes to fetch
  • 5.2.2 Changes to DEC/MAP
  • 5.2.3 Changes to Issue/RF
  • 5.2.4 Other pipeline stages
  • 5.3 Superscalar vs. VLIW; in-order vs. out-of-order
  • 5.4 Simultaneous multithreading for modern architectures
  • 6. Managing contention
  • 6.1 Managing cache and memory contention
  • 6.2 Branch predictor contention
  • 6.3 Managing contention through the fetch unit
  • 6.4 Managing register files
  • 6.5 Operating system thread scheduling
  • 6.6 Compiling for multithreaded processors
  • 6.7 Multithreaded processor synchronization
  • 6.8 Security on multithreaded systems
  • 7. New opportunities for multithreaded processors
  • 7.1 Helper threads and non-traditional parallelism
  • 7.2 Fault tolerance
  • 7.3 Speculative multithreading on multithreaded processors
  • 7.4 Energy and power
  • 8. Experimentation and metrics
  • 9. Implementations of multithreaded processors
  • 9.1 Early machines, DYSEAC and the Lincoln TX-2
  • 9.2 CDC 6600
  • 9.3 Denelcor HEP
  • 9.4 Horizon
  • 9.5 Delco TIO
  • 9.6 Tera MTA
  • 9.7 MIT Sparcle
  • 9.8 DEC/Compaq Alpha 21464
  • 9.9 Clearwater Networks CNP810SP
  • 9.10 ConSentry Networks LSP-1
  • 9.11 Pentium 4
  • 9.12 Sun Ultrasparc (Niagara) T1 and T2
  • 9.13 Sun MAJC and ROCK
  • 9.14 IBM Power
  • 9.15 AMD Bulldozer
  • 9.16 Intel Nehalem
  • 9.17 Summary
  • Bibliography
  • Authors' biographies.

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