Loading...

System-on-chip test architectures: nanometer design for testability

Bibliographic Details
Main Author: Wang, Laung-Terng (ed. by)
Other Authors: Stround, Charles E. Touba, Nur A.
Format: Printed Book
Language:English
Published: Boston Morgan Kaufmann 2008
Subjects:
LEADER 00795nam a2200253 a 4500
001 adlib96000001
003 ViArRB
005 20151026132319.0
008 960221s1955 dcuabcdjdbkoqu001 0deng d
020 |a 9780123739735 
022
040 |a Adlib 
082 |a 621.9 
245 |a System-on-chip test architectures: nanometer design for testability 
250
260 |a Boston  |b Morgan Kaufmann  |c 2008 
300 |a xxxiii, 856p. 
500 |a   
100 |a Wang, Laung-Terng  |e ed. by 
700 |a Stround, Charles E.  |a Touba, Nur A. 
942 |c BK  |6 _ 
653 |a Systems on a chip-Testing  |a Integrated circuits- very large scale integration- Testing 
999 |c 46032  |d 46032 
952 |0 0  |1 0  |4 0  |6 6219_WAN  |7 0  |9 58505  |a UL  |b UL  |d 2010-06-16  |o 621.9 WAN  |p 00059065  |r 2010-06-16  |w 2010-06-16  |y BK